3. Power On Self Test (POST) Beep codes by BIOS manufacturer
Listed below are the BEEP codes associated with the POST of several BIOS manufacturers. BEEP codes are generated PRIOR to the verification of the basic I/O functions required to display an error message/code on the display screen. BEEP codes are ALWAYS hardware related and not caused by software.
If a failure occurs before the PC has determined that it can display information on the screen it announces the failure(s) via BEEP codes through the PC speaker. This allows you to determine the basic failure symptom that cannot be displayed graphically.
⦁ Power supply must exit the power on state, detect PWR OK and release its reset signal.
⦁ CPU must exit the reset state and be able to execute instructions.
⦁ BIOS chip must be accessible for reading data.
⦁ BIOS checksum must be compared. (Valid data in BIOS)
⦁ CMOS must be accessible for reading data.
⦁ CMOS checksum must be compared. (Valid data in CMOS)
⦁ CPU must be able to access memory. (Memory controller, mem bus, mem module)
⦁ I/O bus must be accessible. (I/O controller)
(j) I/O bus must be able to write/read data to the video subsystem. (graphics PCB)
(i) Video system must be able to read from/write to the I/O bus.
(ii) Video RAM must be able to write to/read from video ram, valid data.
If a failure occurs before the PC has determined that it can display information on the screen it announces the failure(s) via BEEP codes through the PC speaker. This allows you to determine the basic failure symptom that cannot be displayed graphically.
⦁ Power supply must exit the power on state, detect PWR OK and release its reset signal.
⦁ CPU must exit the reset state and be able to execute instructions.
⦁ BIOS chip must be accessible for reading data.
⦁ BIOS checksum must be compared. (Valid data in BIOS)
⦁ CMOS must be accessible for reading data.
⦁ CMOS checksum must be compared. (Valid data in CMOS)
⦁ CPU must be able to access memory. (Memory controller, mem bus, mem module)
⦁ I/O bus must be accessible. (I/O controller)
(j) I/O bus must be able to write/read data to the video subsystem. (graphics PCB)
(i) Video system must be able to read from/write to the I/O bus.
(ii) Video RAM must be able to write to/read from video ram, valid data.
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